A Brief Introduction to Neuromorphic Processors

1. Intorduction
The von Neumann architecture is one of the greatest inventions of mankind in the 20th century. However, with the depletion of Moore's law, people need to find a more suitable computing architecture for artificial intelligence tasks that support dense computing. The birth of an integrated neuromorphic computing chip provides a solution. The neuromorphic computing chip liberates the CPU originally limited by the bus bandwidth by using many-core architecture and advanced memory-computing integrated devices ( such as memristors and ferroelectric transistors ), undertaking the heavy neural network inference tasks. Current neuromorphic chips often support spiking neural networks and artificial neural networks in the meantime. This article briefly reviews some neuromorphic processors that have attracted much attention in recent years.
In the late 1980s, M. Ismail and Carver Mead proposed neuromorphic computing. In 1989, P. M. Daniel et al.first reported a fully simulated sum-product neural model, which is made using very large-scale integrated circuit ( VLSI ) technology. In the first decade of the 21st century, a lot of work has been done on neuromorphic chips based on digital, analog, mixed-signal, and FPGA ( programmable gate array ) technologies.
In the 21 st century, when artificial intelligence has passed through the winter, neuromorphic devices have been greatly developed. Many universities and companies have also proposed new neuromorphic chip architectures, including TrueNorth (USA, International Business Machine ), BrainScaleS (Germany, University of Heidelberg), SpiNNaker (UK, University of Manchester), ROLLS ( Switzerland, Zurich Federal Institute of Technology ), Neurogrid (USA, Stanford University ), TianJic (China, Tsinghua University), Loihi (USA, Intel) and so on.
In 2008, HP developed a prototype memristor to simulate synaptic function, which triggered a global artificial synapse boom. By 2012, the neural network simulated by the Blue Brain Project has been able to reach 1 trillion neurons and had a billion synapses. In 2014, IBM's research team constructed a TrueNorth brain-like chip (also known as ' neuromorphic chip, that is, a chip based on ultra-large-scale integrated circuits to simulate human brain function ) with synaptic nuclei as the basic processing unit to achieve ultra-fast and ultra-low energy terminal image stream processing performance greater than 6000 $ frames/second/watt$. The chip is based on a purely digital circuit spiking neural network chip, which can simulate a total of 1 million neurons and 256 million synapses. The system uses a fixed-point operation mode, with the ' event-driven ' operating mode, the entire chip contains 5.4 billion transistors, while the power consumption is only 70 mW. Some of the chips are listed in Table 1. More and more tasks about brain simulation and spiking neural network computing are deployed on brain-like computing chips. It is worth looking forward to the future through these chip scientists can get more inspiration on the study of the human brain.
Table 1: Some Famous neuromorphic devices
Name | parameters | Core |
IBM TrueNorth | 1M neurons, 256M synapses, 73mW power | Digital circuit |
ETH ROLLS | 256 neurons, 256 constant synapses, 64kprogramable synapses,64k plausible synapses | sub-threshold mixed analog circuit |
Intel Loihi | 14nm+33MB SRAM,128neural cores with 3 x86CPU | Digital circuit |
Tianjic 2 | 156 cores array, supporting SNN+ ANN | Analog+Digital circuit |
2. Development of famous neuromorphic devices
2.1. Loihi and Loihi2 of Intel

Figure 1: Comparison of 1st generation loihi and the second generation Loihi chips. There are now plenty of applications on Loihi 1 in the field of artificial intelligence or computational neuroscience.
In September 2017, Intel unveiled its first neuromorphic chip, Loihi, which supports autonomous learning. Like the human brain, the Loihi chip can transmit information through pulses or spikes, and automatically adjust synaptic strength. Through various feedback information in the environment, autonomous learning and instruction are performed. It can use a small amount of data to learn independently and make inferences. It will become more intelligent over time and does not need to be trained in a traditional way with a large amount of data. At the time, however, Loihi was only based on FPGA simulation. At CES 2018, Intel officially released the Loihi chip with full functionality and announced that Loihi is fully operational and will share the Loihi chip with leading universities and research institutions for more complex datasets and issues.
The first generation of Loihi is based on Intel's 14 nm process, with a core area of 60 mm. It consists of 128 Neuromorphic Cores ( neuromorphic cores with 208 KB cache per core ) + 3 low-power Intel X86 cores, with 128,000 neurons and 128 million tentacles. Each neuron can have 24 variable states.
The latest Loihi 2 is upgraded to Intel 4 process ( equivalent to TSMC 4nm ), and the core area is reduced to 31 mm. It integrates 128 Neuromorphic Cores ( each core has 192 KB cache ) and 6 low-power Intel X86 cores. Thanks to the significant improvement of the process technology, the number of neurons in Loihi 2 has increased to 1 million, which is 7.8 times that of the first generation, but the number of synapses has been slightly reduced to 120 million. Loihi 2 can assign up to 4096 variable states according to the requirements of the neuron model. These improvements make the processing speed of Loihi reach 10 times that of the first generation Loihi.
Thanks to this Blog for sorting out the history of Loihi chips
2.2. IBM-TrueNorth

Figure 2: An overview or IBM ' s TrueNorth Chip
TrueNorth is with a 28 nm process, it has 5.4 billion transistors and is one of the largest transistor chips in IBM. When simulating complex recurrent neural networks, TrueNorth has a power consumption of less than 100 and a power density of 20 . Different from the mainstream von Neumann architecture, TrueNorth has a highly parallel and flexible architecture, supports distributed, modular, scalable, fault-tolerant, integrates computing, communication, and memory, and has no internal clock. Objectively speaking, Zhenbei from the scale, architecture, efficiency, scalability, and chip design technology, has produced innovation.
Under the total power of 70 , the TrueNorth chip runs a typical biological real-time loop network, which is four orders of magnitude lower than that of traditional computers running the same network. It supports multi-target detection and classification applications, 240x400 pixel 3-color video input, 30 frames per second, chip power consumption of 65 , each synaptic event requires 26 picojoules, breaking the minimum recorded energy of large-scale neuromorphic systems at that time, which is 5 orders of magnitude lower than that of von Neumann computers. It has power density, equivalent to the cortex, which is three to four orders of magnitude lower than that of CPU's ( ). At present, most of the neuromorphic chips are inherited from IBM architecture, the industry has also given some support.
2.3. Tianjic2 and TianjicX of CBICR, Tsinghua

Figure 3: A schematic diagram of the internal structure of the Tianjic. The synapses are composed of crossbar structure, which can well support the hybrid programming of ANN and SNN.
The second generation of the Celestial Robotic Caliber developed by Tsinghua University adopts a new architecture of heterogeneous fusion, which supports the hybrid paradigm of ANNs and SNNs. It is the first attempt to integrate the two computing methods into a chip architecture, complement each other, and integrate multi-modal information to establish a new artificial intelligence system. The fusion of multimodal information is an important contribution of the chip in exploring the road of general artificial intelligence. It has more than 10 million synapses and a clock frequency of 300 MHz. Supports mixed programming of MLP, CNN, SNN, etc. The design of the celestial movement takes into account a variety of hardware constraints, including the need to enable a variety of networks to be implemented in one chip ( including bionic-based spiking neural network SNN, ANNs supported by connectionism, etc. ), so as to achieve a broader use prospect. Secondly, to be able to meet the actual needs of the premise of compression network size, which is based on manufacturing costs, energy consumption, and overall performance considerations. The design of the celestial movement is still based on bionics and brain science. At the bottom, the celestial core uses electrons to simulate dendrites, axons, and cell bodies in synapses. At the neuron cluster level, the cross-bar structure is used to form the kernel. Using chips and chip arrays to complete the construction of large-scale neural networks and ultra-large-scale neural networks.
In 2021, Tsinghua has published a new generation of Tianji chip, named TianjicX. It is specially designed for robotic applications, which are aimed at processing different tasks asynchrony with extremely low power consumption. Interestingly, through cooperation with many-core architecture chips, different functions and different types of neural networks can run asynchronously on the same chip in parallel. The article used a cat-and-mouse DEMO to demonstrate how to use the chip.

Figure 4: Multiple algorithms run asynchronously in parallel on the TianjicX chip, supporting a simple robotic task
3. Discussion
At present, the representative work of AI chips can be summarized into two mainstream directions : the first direction is the deep learning accelerator, which mainly supports the artificial neural network ( ANN ) represented by the convolutional neural network CNN ; the second direction is brain-like computing / neuromorphic chip, which mainly supports spiking neural network ( SNN ).
Compared with ANN, SNN has more information coding methods, such as time domain coding, space-time coding, group coding, bayesian coding, time delay coding, sparse coding, etc. Therefore, SNN has great potential in dealing with complex Spatio-temporal information and multi-modal information tasks. On the other hand, the discontinuity of the SNN neuron model, the complexity of Spatio-temporal coding, and the uncertainty of network structure makes it difficult to describe the whole network mathematically and construct an effective and general learning algorithm, which limits its computational scale and accuracy.
The above deep learning accelerators and brain-like computing chips neuromorphic chips have their own advantages and disadvantages : the former has high computational accuracy, is easy to implement back propagation, and the technology development has matured, but the support for the time domain is weak ; the latter is rich in coding methods, has potential advantages in processing tasks related to timing, and has the advantages of dynamic plasticity and connection sparsity. It can achieve ultra-low power consumption by realizing sparsity and event-driven mode, but faces the constraints of training scale, speed, and performance. Therefore, the two AI chips can achieve complementary advantages, but it is difficult to replace each other.
Reference
7-11 are not cited in the arcticle, only provided for further reading.
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- [2] Davies M, Srinivasa N, Lin T H, et al. Loihi: A neuromorphic many-core processor with on-chip learning. IEEE Micro, 2018, 38(1):82-99.
- [3] Tao L, Liu S, Ling L, et al. Dadiannao: A neural network supercomputer. IEEE Transactions on Computers, 2016, 66(1):1-1.
- [4] Pei J, Deng L, Song S, et al. Towards artificial general intelligence with hybrid tianjic chip architecture. Nature, 2019, 572(7767):106-111.
- [5] Merolla, Paul A et al. "A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface." Science, vol. 345, no. 6197, 2014, pp. 668-673.
- [6] Esser, Steven K et al. "Convolutional Networks for Fast, Energy-Efficient Neuromorphic Computing." Proceedings of the national academy of sciences, vol. 113, no. 41, 2016, pp. 11441-11446.
- [7] Benjamin, Ben Varkey et al. "Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations." Proceedings of the IEEE, vol. 102, no. 5, 2014, pp. 699-716.
- [8] Chen, Yu-Hsin et al. "Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks." IEEE Journal of Solid-State Circuits, vol. 52, no. 1, 2016, pp. 127-138.
- [9] Qiao, Ning et al. "A Reconfigurable on-Line Learning Spiking Neuromorphic Processor Comprising 256 Neurons and 128k Synapses." Frontiers in Neuroscience, vol. 9, 2015, p. 141.
- [10] Moradi, Saber et al. "A Scalable Multicore Architecture with Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (Dynaps)." IEEE Transactions on Biomedical Circuits and Systems, vol. 12, no. 1, 2017, pp. 106-122.
- [11] Ma, De et al. "Darwin: A Neuromorphic Hardware Co-Processor Based on Spiking Neural Networks." Journal of Systems Architecture, vol. 77, 2017, pp. 43-51.
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